As integrated circuits are produced with greater and greater levels of circuit density, efficient testing schemes that guarantee very high fault coverage while minimizing test costs and chip area overhead have become essential. Particularly, verifying at-speed performance of integrated circuits is important to ensure a satisfactory shipped part quality level (SPQL). In past, at-speed performance of integrated circuits was typically verified using functional tests. However, as the complexity and density of circuits continues to increase, high fault coverage of several types of fault models becomes more difficult to achieve with traditional testing paradigms. For example, it is not feasible to develop functional tests for today's multi-million gate designs to achieve satisfactory defect coverage due to the prohibitive cost of such development. Conventionally, the scan-based delay testing approach is used as a low-cost alternative to functional testing for verifying at-speed performance of integrated circuits.
Timing failures caused by delays may result in circuitry logic failure and eventually lead to a system failure. Thus, in the scan-based delay testing approach, performance failures are modeled as delay-causing faults and test patterns are generated by an automatic test pattern generator (ATPG).
Transition delay fault and path delay fault models are known to provide a good coverage of delay-causing faults. The transition delay fault (TDF) model targets every node in the design for a slow-to-rise and a slow-to-fall delay fault whereas the path delay fault model targets the cumulative delay through paths in the circuit. The TDF model is commonly used in the industry since it is simple and existing ATPG algorithms can be easily adapted to generate tests for TDF faults.
One of the challenges faced by several companies in the industry is the increased cost of TDF testing because the TDF model requires a large number of patterns and a large amount of scan memory. Some companies have adopted truncation of patterns to reduce the number of patterns and testing cost. However, the truncation of pattern may have a few drawbacks. For example, it may affect quality of ICs. The quality of ICs can be measured in many ways, but in general it is represented as the number of defective parts per the number of units shipped. Typically, the quality of ICs manufacturing is measured in terms of yield. 97% yield may indicate that 3% of ICs are defective and 97% of ICs are non-defective. Additionally, the quality of ICs may be represented by Defect Per Million (DPM) which is a measure of how many malfunctioned ICs are incorrectly found to be as functioned ICs due to the TDF tester inaccuracy. It is known to the art that the truncation of pattern may result in increased DPM and/or poor yield, which is an indirect cost to customers.
Therefore, it would be desirable to provide a method and system for pruning test patterns to reduce number of test patterns and test costs while it does not compromise the quality of ICs.